AFE7950EVM: Serdes FIFO error in AFE750+TRF1208 EVM module

Tool/software:

Dear Team, 

I am trying to take the DAC output from AFE7960+TRF1208 EVM used along with TSW1457EVM.

I have given LMK clock as 3GHz at 10 dBm and the AFE reference clock as 12 GHz at 10 dBm according to our requirement. The input voltage given for the EVM module is 5.5V@4A and for the FPGA board TSW14J57 is 12V@4A .

But while running the script in latte, the following attached error is observed.

I tried the method of clicking “Send” for the DAC pattern multiple times in HSDC and running the command “AFE.adcDacSync(1)”. But the same error was observed

Please suggest a solution for this.